By Erik Larsson
SOC try layout and its optimization is the subject of Introduction to complex System-on-Chip try layout and Optimization. It supplies an advent to trying out, describes the issues on the topic of SOC checking out, discusses the modeling granularity and the implementation into EDA (electronic layout automation) instruments. The ebook is split into 3 sections: i) attempt innovations, ii) SOC layout for attempt, and iii) SOC attempt functions. the 1st half covers an creation into try out difficulties together with faults, fault forms, design-flow, design-for-test concepts similar to scan-testing and Boundary test. the second one a part of the e-book discusses SOC similar difficulties reminiscent of approach modeling, try out conflicts, strength intake, try entry mechanism layout, attempt scheduling and defect-oriented scheduling. eventually, the 3rd half makes a speciality of SOC purposes, equivalent to built-in attempt scheduling and TAM layout, defect-oriented scheduling, and integrating attempt layout with the middle choice process.
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Extra info for Introduction to Advanced System-on-Chip Test Design and Optimization (Frontiers in Electronic Testing)
The best solution, found using exhaustive search in the local neighborhood (steepest decent), is used as the next solution. In practice the search in the local neighborhood can be terminated at first improvement. The first improvement makes use of less computational cost compared to the steepest decent. However, in steepest decent each iteration creates a better solution, which can lead to less required iterations, hence less computational cost, compared to using first improvement. In order to avoid getting stuck at local optimum, a larger neighborhood can be used.
In order to detect a delay fault, two test vectors are used. The first vector initializes the design and the second vector, applied in the consecutive clock cycle, captures the fault. Furthermore, it is important that the testing is performed at system speed, otherwise the timing fault is most likely not present. A disadvantage of the scan technique is that it is difficult to apply the two vectors in consecutive clock cycle. The scan technique requires test vector shift-in, capture, and then shift-out.
E. one test is performed when all scan-chains are loaded/unloaded. Long scan chain lead to long testing times. In order to reduce the test application time, a higher number of scan chains can be used, which reduces the loading/unloading time since it is performed concurrent over all scan chains. In a test-per-clock scheme there is one test per clock cycle. 3 LOCST (LSSD On-Chip Self-Test) In the LOCST (LSSD On-Chip Self-Test) architecture the test data is transported to the circuit under test using a boundary scan chain .